A reduction in power consumption of electronic devices has been highly required. Thus, a reduction in power consumption of integrated circuits (ICs) such as CPUs is a major challenge in circuit design. The power consumption of ICs is broadly classified into operating power consumption (dynamic power) and non-operating (standby) power consumption (static power). Dynamic power increases when an operating frequency is increased for high performance. Static power is power consumed mostly by the leakage current of transistors. Examples of leakage current include subthreshold leakage current, gate tunnel leakage current, gate-induced drain leakage (GIDL: Gate-induced drain leakage) current, and junction tunnel leakage current. These leakage currents increase in accordance with scaling down of transistors. Thus, an increase in power consumption is a large barrier to high performance and high integration of ICs.
In order to reduce power consumption of a semiconductor device, circuits that do not need to operate are stopped by power gating or clock gating. Power gating has the effect of eliminating standby power because supply of power is stopped. In order to perform power gating in a CPU, it is necessary to back up contents stored in a register or a cache to a nonvolatile memory.
A memory circuit capable of retaining data even when power is off, which takes advantage of a feature of extremely low off-state current of a transistor whose active layer is formed using an oxide semiconductor (Oxide Semiconductor) (hereinafter, such a transistor is referred to as an “oxide semiconductor transistor” or an “OS transistor”), has been proposed. For example, Non-Patent Document 1 discloses an OS-SRAM (static random access memory) including a backup circuit that includes an OS transistor. Non-Patent Document 1 discloses that in a microprocessor mounted with an OS-SRAM enables power gating in a short break-even time (BET) without affecting normal operation.